The present invention relates to a nonvolatile flash memory in which information is rewritable by electrical erasing/writing and a microcomputer incorporating the same.
JP-A-1-161469 (Laid-open on Jun. 26, 1989) describes a microcomputer having, as a programmable nonvolatile memory, an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) carried on a single semiconductor chip. Data and programs are held in such an on-chip nonvolatile memory of the microcomputer. Since information stored in the EPROM is erased by means of ultraviolet rays, the EPROM must be removed from a system on which it is mounted in order for the EPROM to be rewritten. The EEPROM can be erased and written electrically and therefore information stored therein can be rewritten with the EEPROM mounted on a system. However, memory cells constituting the EEPROM must be comprised of, in addition to memory devices such as MNOSs (metal nitride oxide semiconductors), selecting transistors and hence the EEPROM requires a relatively large chip occupation area being, for example, about 2.5 to 5 times as large as that of the EPROM.
JP-A-2-289997 (Laid-open on Nov. 29, 1990) describes a simultaneous erasing type EEPROM. This simultaneous erasing type EEPROM can be described as operating as a flash memory, such as described in the present specification. In the flash memory, information can be rewritten by electrical erasing and writing, each memory cell can be constructed of a single transistor as in the EPROM and, functionally, all memory cells or a block of memory cells can be erased simultaneously by electrical erasing. Accordingly, in the flash memory, information stored therein can be rewritten with the flash memory mounted on a system, the time for rewrite can be shortened by virtue of its simultaneous erasing function and contribution to reduction of the area occupied by a chip can be accomplished.
U.S. Pat. No. 5,065,364 (issued on Nov. 12, 1991) shows a flash memory of the type in which an array of electrically erasable and rewritable memory cells having control gates, drains and sources is divided into a plurality of memory blocks in a unit of data line, source lines in common to each block are led out and a voltage complying with an operation is applied separately to a source line by means of a source switch provided in each source line. At that time, ground potential is applied to the source line of a block selected for writing. A voltage VDI of, for example, 3.5V is applied to the source line of a block not selected for writing. The voltage VDI guards against word line disturbance. The word line disturbance referred to herein is a phenomenon that for example, in a memory cell having a word line conditioned for selection and a data line conditioned for unselection, the potential difference between the control gate and floating gate is increased and as a result, electric charge is discharged from floating gate to control gate to decrease the threshold of the memory cell transistor.
JP-A-59-29488 (laid-open on Feb. 16, 1991) and JP-A-3-78195 (laid-open on Apr. 3, 1991) describe an ultraviolet light-erasable EPROM in which sources of memory cells connected with the same word line are connected in common and a source potential control switch is provided for the commonly connected sources. JP-A-3-78195 (laid-open on Apr. 3, 1991) describes an ultraviolet light-erasable EPROM in which sources of memory cells connected with adjacent two word lines are connected in common and a source potential control switch is provided for each adjacent two word lines. Each of the inventions disclosed in these three references is intended to provide a solution to a problem of erroneous writing/reading caused by leak current from an unselected memory cell in an EEPROM.
U.S. application Ser. No. 07/942,028 filed Sep. 8, 1992, which is a continuation application of U.S. application Ser. No. 07/568,071 filed Aug. 16, 1990, discloses a structure of a flash memory in which sources of memory cells are connected in common for the purpose of preventing a word line disturb problem for a writing operation.
Meanwhile, JP-A-3-14272 (laid-open on Jan. 22, 1991), JP-A-3-250495 (laid-open on Nov. 8, 1991) and JP-A-2-241060 (laid-open on Sep. 25, 1990) describe division of a memory cell array in a unit to data line.
The present inventors have first studied the fact that a flash memory is carried on a microcomputer to find out the following points.
(1) Programs and data are stored in a ROM incorporated or built in the microcomputer. Data is classified into data of a large capacity and data of a small capacity. When the programs and data are to be rewritten, the former data is typically rewritten in a large unit of severals of tens of KB (kilobyte) and the latter data is typically rewritten in a small unit of severals of tens of B (byte). At that time, if the flash memory is erased in a unit of chip batch or in a unit of memory block of the same size, inconvenience that the erase unit matches with a program area but is excessively large for a data area to impair ease of use thereof may occur or the converse case may occur.
(2) When part of information held in the flash memory is desired to be rewritten after the microcomputer is mounted on a system, it suffices to use part of the memory block holding the information of interest as an object to be rewritten. But if all simultaneously erasable memory blocks have an equal storage capacity, then even when rewrite of only a smaller amount of information than the storage capacity of a memory block is desired, the memory block of a relatively large storage capacity must be erased simultaneously and thereafter write is carried out over the whole of the memory block in question, with the result that time is consumed wastefully for rewrite of information not substantially required to be rewritten.
(3) Information to be written into the flash memory is determined in accordance with the system to which the microcomputer is applied but efficiency may sometimes be degraded when the information is all written from the beginning with the microcomputer of interest mounted on the system.
(4) When the flash memory is rewritten with the microcomputer mounted, it sometimes suffices that only part of information of a memory block, standing for an object to be rewritten, is rewritten. But even in this case, if information to be written into the whole of the memory block which has been erased simultaneously is all received sequentially externally of the microcomputer and rewritten, all of the information to be written into the whole of the memory block of interest will have to be received from the outside in spite of the fact that it suffices to rewrite only part of information of the memory block to be rewritten, and transfer, from the outside, of information not substantially required to be rewritten, that is, information held internally in advance of rewrite must be repeated, resulting in wastefulness of transfer of information for partial rewrite of the memory block.
(5) Because of information storing mechanism, the time for rewriting the flash memory through simultaneous erasing is far longer as compared to a memory such as RAM (random access memory) and so the flash memory cannot be rewritten on real time base in synchronism with machine control operation by the microcomputer.
The present inventors have studied the division of memory blocks in a unit of data line to find that the size of the minimum memory block can be decreased more easily by division into memory blocks in a unit of word line and using sources in common in a block and this is advantageous also from the standpoint of improving ease of use of the flash memory built in the microcomputer as studied firstly. When the division into memory blocks in a unit of data line is employed, all memory cells of a selected block for writing arranged in line and having drains connected to a data line applied with a write high voltage suffer from data line disturbance. The data line disturbance is a phenomenon that for example, in a memory cell associated with a word line not rendered to be selected and a data line rendered to be selected for writing, an electric field between the source and drain is increased, so that hot holes are injected from drain to floating gate to decrease the threshold of the memory cell transistor.
A major object of the invention is to provide a microcomputer incorporating a flash memory which is easy to use. More particularly, a first object of the invention is to provide a microcomputer capable of making highly efficient a processing of initial write of information into the built-in flash memory. A second object of the invention is to improve rewrite efficiency of part of information held in some of memory blocks of the flash memory by eliminating wastefulness of write operation after simultaneous erasing of the memory blocks of interest. A third object of the invention is to improve rewrite efficiency by eliminating wasteful transfer operation, from the outside, of write information necessary for partial rewrite of a memory block. A fourth object of the invention is to change information held in the flash memory on real time base in synchronism with control operation by the microcomputer.
Further, the invention has for its object to provide a flash memory in which the minimum size of memory block obtained by using sources in common in an electrically rewritable nonvolatile memory device can be decreased. Still another object is to prevent an erroneous operation due to data line disturbance in a unselected memory block for writing from occurring when formation of memory blocks is effected in a unit of word line.
Major aspects of the present invention will now be described.
More specifically, a microcomputer comprises, on a single semiconductor chip, a central processing unit and a nonvolatile flash memory in which information to be processed by the central processing unit is rewritable by electrical erase and write, and the microcomputer is provided with an input terminal of an operation mode signal for designating a first operation mode in which rewrite of the flash memory is controlled by a circuit built in the semiconductor chip and a second operation mode in which it is controlled by a unit provided externally of the semiconductor chip.
When the central processing unit performs rewrite control in accordance with designation of the first operation mode, a rewrite control program to be executed by the central processing unit may be held in a mask ROM or a rewrite control program precedently stored in the flash memory may be transferred to a RAM and executed.
The fact that the amount of information to be stored in the flash memory in accordance with an application differs in accordance with the kind of the information such as for example a program, a data table or control data is taken into consideration. Then, in order that upon rewrite of part of information held in some of memory blocks of the flash memory, efficiency of rewrite can be improved by eliminating wastefulness of write operation after simultaneous erasing of the memory blocks of interest, a plurality of memory blocks having mutually different storage capacities may be allotted each for a simultaneously erasable unit in the flash memory.
When rewrite of the flash memory is controlled internally and externally of the microcomputer, in order for a memory block to be erased simultaneously can be designated easily, a register in which information for designating the memory block to be erased simultaneously is rewritably held may be incorporated in the flash memory.
When the built-in flash memory has, as a simultaneous erase unit, a plurality of memory blocks having mutually different storage capacities, in order that the built-in RAM can be utilized as a working area or a data buffer area for rewrite of memory block, a memory block having a storage capacity set to be smaller than that of the built-in RAM may be provided. In this case, for the sake of improving efficiency of rewrite by eliminating wastefulness of transfer operation, from the outside, of write information necessary for partial rewrite of the memory block, information held in the memory block having a storage capacity smaller than that of the built-in RAM may be transferred to the built-in RAM, all or part of the transferred information may be renewed on the RAM and the memory block of interest may be rewritten with renewed information. Further, upon tuning of data such as control data held in the flash memory, in order that information held in the flash memory can be changed on real time base in synchronism with control operation by the microcomputer, a processing may be effected wherein addresses of a specified area of the built-in RAM are controllably changed and arranged so as to overlap addresses of the memory block having the smaller storage capacity than the built-in RAM, that is, changed and arranged so that the overlapped RAM may be accessed when the memory block is accessed and after working has been done at the specified address, the arranged address of the RAM is restored to the original state and the contents of the memory block is rewritten with the information at the specified address of the RAM.
In order to decrease the minimum block size more easily as compared to the case where memory blocks are formed in a unit of data line, memory blocks are defined by connecting a common source line to memory cells having their control gates coupled to a single or a plurality of word lines in a unit of word line.
At that time, to take care of data line disturbance in an unselected memory block for writing, voltage output means is adopted which can control, in a unit of memory block, potential of the source line to first potential and to second potential of higher level than that of the first potential upon write operation, whereby the voltage output means applies the first potential to a source line of a memory block including memory cells having an associated data line and an associated word line applied with predetermined voltages so as to be selected for writing and applies the second potential to a source line of a memory block including memory cells having an associated data line applied with the predetermined voltage and an associated word line not applied with the predetermined voltage so as not to be selected for writing.
In order to improve ease of use in the formation of memory blocks in a unit of word line, a plurality of memory blocks include a single or a plurality of large memory blocks associated with a relatively large number of word lines and a single or a plurality of small memory blocks associated with a relatively small number of word lines.
At that time, in order to minimize the data line disturbance time, the large memory block and the small memory block have data lines in common and arranged separately in line, a selection circuit for selecting a data line upon write and read operations is arranged near the large memory block, a transfer gate circuit is inserted in data lines which are associated in common with the large memory block and small memory block, and a control circuit is provided which cuts off the transfer gate circuit upon write of the large memory block.
According to the above-mentioned aspects of the invention, when information is initially written into the flash memory in the phase preceding mounting of the microcomputer according to the invention, the information can be written efficiently under the control of the external write device such as a PROM writer by designating the second operation mode.
For example, programs, data tables or control data are written into the plurality of memory blocks having mutually different capacities and defined each as a simultaneously erasable unit, in accordance with a storage capacity of each memory block.
When the microcomputer is mounted on the system and thereafter the flash memory is rewritten, the first operation mode is designated to cause, for example, the central processing unit built in the microcomputer to execute control of rewrite. In this case, data of a relatively large information amount can be written in a memory block of a relatively large storage capacity and data of a relatively small information amount can be written in a memory block of a relatively small storage capacity. Namely, a memory block having a storage capacity meeting the information amount to be stored can be utilized. Accordingly, even when a given memory block is erased simultaneously for rewrite of part of information held in the flash memory, such wastefulness that an information group substantially not required to be rewritten is erased concurrently and thereafter written again can be prevented as far as possible.
Especially, when of the plurality of memory blocks, a memory block having a storage capacity set to be smaller than that of the built-in RAM is provided, this memory block may be utilized as a work area or a data buffer area for rewrite of memory block. More particularly, when the flash memory is rewritten with the microcomputer mounted, information in a memory block to be rewritten is transferred to the built-in RAM, only partial information to be rewritten is received from the outside and rewritten on the RAM and then the flash memory is rewritten, whereby transfer, from the outside, of information held internally in advance of rewrite and not required to be rewritten need not be repeated, so that wastefulness of information transfer for partial rewrite of the memory block can be eliminated. Further, in the flash memory, the time for simultaneously erasing a small memory block is not so short that the flash memory per se can be rewritten on real time base in synchronism with control operation by the microcomputer. But, by utilizing the built-in RAM as a work area or a data buffer area for rewrite of memory block, the same data as that rewritten on real time base can eventually be obtained in the memory block.
When memory blocks are defined each in a unit of word line, the minimum memory block has a storage capacity which corresponds to that of one word line, regardless of the number of parallel input/output bits. Contrary to this, when memory blocks are defined each in a unit of data line, the minimum memory block has a storage capacity corresponding to the number of data lines which in turn corresponds to the number of parallel input/output bits. This signifies that the storage capacity of the minimum memory block can be reduced more easily when memory blocks are defined in a unit of word line and especially in the case of a memory incorporated in the microcomputer wherein input/output of data is carried out in a unit of byte or word, the minimum size of memory block can be reduced drastically. This contributes to further improvement in ease of use of the flash memory built in the microcomputer and consequently improvement in efficiency of rewrite of small scale data in a unit of memory block.
In a region near the source side end of the drain of a nonvolatile memory device, electron and hole pairs are generated owing to a tunnel phenomenon between bands. In this case, when a relatively large electric field is generated between the source and drain, holes of the electron and hole pairs are accelerated by the electric field to turn into hot holes. The hot holes are injected to the floating gate through a tunnel insulating film. This state is referred to as data line disturbance and when the data line disturbance affects the device for a long time, the threshold of the memory device is decreased and there results an undesirable change of stored information which leads to an erroneous operation (data line disturbance fault). In an unselected block for writing, by applying second potential such as data line disturbance prevention voltage to a source line of a memory cell to raise source potential, an electric field between the drain and source is weakened, thereby ensuring that holes of electron and hole pairs generated near the drain can be prevented from turning into hot holes to prevent a decrease in the threshold of memory transistor.
For prevention of the data line disturbance fault, minimization of the data line disturbance time (the time for exposure to the data line disturbance state) is effective. In this case, the data line disturbance time affecting a small memory block owing to write concomitant with rewrite of a memory block having a large storage capacity is relatively increased in comparison with the converse case. In view of this fact, by adopting an arrangement in which with respect to an intervening transfer gate circuit, memory blocks on the side of a Y selection circuit are formed of large memory blocks and memory blocks on the opposite side are formed of small memory blocks, the data line disturbance time affecting memory cells of the memory blocks relatively near the Y selection circuit owing to write of the memory block relatively remote from the Y selection circuit can be reduced drastically as compared to the case of the converse arrangement of large memory blocks and small memory blocks. By virtue of this arrangement relation between the large memory blocks and small memory blocks, erroneous operation due to data line disturbance can further be suppressed.
According to still another aspect of the present invention, there is provided a microcomputer comprising a central processing unit, an electrically rewritable flash memory, flash memory rewriting I/O port means capable of being coupled to a ROM writer for rewriting the flash memory, switch means located between the central processing unit and the flash memory, and a rewriting mode decision means responsive to an externally supplied operation mode signal for controlling the switch means and the flash memory rewriting I/O port means, the central processing unit, the flash memory, the flash memory I/O port means, the switching means and the rewriting mode decision means being formed in a single semiconductor chip.
According to still another aspect of the present invention, there is provided there is provided an electrically rewritable flash memory device comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns, each of the memory cells including a non-volatile memory element having first and second semiconductor regions formed in a first surface portion of a semiconductor substrate, a floating gate formed over and insulated from a second surface portion of the semiconductor substrate between the the first and second semiconductor regions, and a control gate formed over and insulated from the floating gate;
a plurality of first conductors extending in parallel with one another in a row direction over the semiconductor substrate, control gates of memory cells in one row being connected in common to one first conductor;
a plurality of second conductors extending in parallel with one another in a column direction over the semiconductor substrate, first semiconductor regions of memory cells in one column being connected in common to one second conductor;
a plurality of common conductors extending in the row direction over the semiconductor substrate, second semiconductor regions of at least two rows of memory cells being connected in common to one common conductor such that the at least one row of memory cells having their second semiconductor regions connected in common to one common conductor form a memory block, memory blocks so formed having different memory capacities;
a plurality of common voltage control circuits formed in the substrate, one provided for each of the memory blocks, for generating a common voltage assuming at least first and second voltage values; and
a control circuit formed in the substrate for generating a control signal indicating which of the memory blocks is subjected to an erasing/writing operation, the control signal being supplied to the plurality of common voltage control circuits so that individual common voltage control circuits apply to their associated common conductors common voltages each having one of the first and second voltage values depending on the control signal to effect a writing operation with a common voltage of the second voltage value applied to a common conductor for a memory block which does not contain a memory cell selected for the writing operation and to effect a simultaneous erasing operation with a common voltage of the first voltage value applied to a common conductor for a memory block selected for a simultaneous erasing operation.